As known in the art, through-substrate vias (referred to herein as TSVs), which are commonly referred to as through-silicon vias, are vertical electrical connections that extend from one of the electrically conductive levels formed on the top surface of a wafer or IC die (e.g., contact level or one of the metal interconnect levels) to the backside (bottom) surface. As a result, the TSV comprising device can be bonded face-up and utilize vertical electrical paths to couple to other IC devices (e.g., on a die, wafer) or to mount to a package substrate. The vertical electrical paths are significantly shortened relative to conventional wire bonding technology, generally leading to significantly faster device operation.
Regarding fabrication of TSVs, in a typical via-first process, vias are formed to a depth (e.g., 100 to 200 μm) that is significantly less than the full wafer thickness (e.g., 300 to 800 μm) using chemical etching, laser drilling, or one of several energetic methods, such as Reactive Ion Etching (RIE). Once the vias are formed, they are generally framed with a dielectric liner to provide electrical isolation from the surrounding substrate, and then made electrically conductive by filling the vias with an electrically conductive filler material (e.g., copper, tungsten, or doped polysilicon) to form embedded TSVs. The bottom of the embedded TSV is generally referred to as an embedded TSV tip. Since most electrically conductive filler materials are metals that can degrade minority carrier lifetimes (e.g., copper or tungsten), a barrier layer is generally deposited on the dielectric liner. In the case of an electroplated metal (e.g., copper) process, a seed layer is generally added after the barrier layer.
A backgrinding step is then conventionally used to thin the wafer by removing a sufficient thickness of the substrate (e.g., 50 to 300 μm) from the bottom surface of the wafer to reach the embedded TSV tip to expose the electrically conductive filler material at the distal end of the TSV tip. The high substrate removal rate provided by the backgrinding process is needed for manufacturability of the thinning process due to the large substrate thickness (e.g., several hundred μms) being removed. A subsequent polish step, (e.g. chemical mechanical polish (CMP)) can be used to remove on the order of several μms from the bottom surface of the substrate in an attempt to reduce the mechanical damage and contamination generated by the backgrinding process. Alternatively or additionally, a wet or dry chemical etch can be used to reduce the mechanical damage and the contamination resulting from the backgrinding.
The distal end of the completed TSV tip is conventionally flush with the bottom surface of the substrate. A solder bump or other electrically conductive finish may be added to the TSV tip prior to assembly to a workpiece which protrudes outward a relatively short distance from bottom surface of the substrate.